The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including a vertical transistor having a bottom spacer structure that is present on a bottom source/drain region, wherein the bottom spacer structure includes a silicon dioxide spacer and a silicon nitride spacer. The present application also provides a method of forming such a semiconductor structure.
Conventional vertical transistors are devices where the source-drain current flows in a direction normal, i.e., vertical, to the substrate surface. In such devices, a vertical semiconductor pillar defines the channel with the source and drain located at opposing ends of the semiconductor pillar. One advantage of a vertical transistor is that the channel length is not defined by lithography, but by methods such as epitaxy or layer deposition, which enable precise dimensional control. As such, vertical transistors are an attractive option for technology scaling for 5 nm and beyond.
In conventional vertical transistor device architecture, it is difficult to remove the bottom spacer material from the sidewalls of the vertical semiconductor pillar without removing portions of the bottom spacer material that are present above the bottom source/drain region that is formed at the footprint of the vertical semiconductor pillar. Instead, conventional vertical transistors typically have a step coverage of the bottom spacer material along the sidewalls of the vertical semiconductor pillar. Such step coverage may lead to variation in channel length and junction location. As such, there is a need for providing a semiconductor structure including a vertical transistor in which the step coverage of the bottom spacer is minimized thus reducing the variation in channel length and junction location of the vertical transistor.